In deep sub-micron integrated circuit technology, an embedded static random access memory (SRAM) device has become a popular storage unit of high speed communication, image processing and system-on-chip (SOC) products. For example, a fin transistor, such as a fin field-effect transistor (FinFET), is introduced to replace a planar transistor and is used to form a SRAM device. The fin transistor has a channel (referred to as a fin channel) associated with a top surface and opposite sidewalls. The fin channel has a total channel width defined by the top surface and the opposite sidewalls. In advanced technology nodes, such as 32 nm or beyond, a FinFET is advantageous to the planar transistor because of its lower leakage.
In a SRAM cell, such as a SRAM cell with 6 transistors (6T-SRAM), the layout with the beta ratio close to 1 provides a reduced cell size. In this situation, the pull-down devices and the pass-gate devices have a same device dimension. In a SRAM cell using FinFETs, a single fin size for all transistors can provide the minimized cell size. As to a high speed application, equal numbers of pull-down devices and of pass-gate devices provide a proper tradeoff between the cell speed and the cell size. In this situation, the beta ratio is equal to or less than one. However, this will lead to various beta ratio associated issues such as current crowding. Therefore, it is desired to have a new structure and a method to address the above issues.